The present invention relates generally to computer systems and, more particularly, to a method for detecting errors in instructions which are used to test, monitor and/or observe a plurality of JTAG components interconnected into a JTAG boundary scan path for JTAG operations.
The Institute of Electrical and Electronics Engineers, IEEE, has standardized a serial test bus for testing integrated circuit components, their interconnections on a printed circuit board and for observing or modifying circuit activity during normal operation of the components. The standardized bus is designated as the IEEE Std 1149.1 and was developed by a Joint Test Action Group, JTAG, composed of members from both Europe and North America such that it is often referred to as an 1149.1 or a JTAG bus.
Instructions are used to control JTAG circuitry in JTAG components and it is recognized that errors in these instructions need to be detected to prevent operation of the JTAG circuitry in an undesirable manner. For example, instruction errors can be detected by means of the addition of a parity bit to each of the instructions used in a JTAG system. Other error detection arrangements can also be used. Unfortunately, no matter how errors are detected in the JTAG instructions, the detection of the errors must be communicated back to the JTAG system controller to prevent undesirable system operation. The communication back to the JTAG controller or feedback conventionally takes the form of undesirable additional pins or connections on the JTAG components.
Accordingly there is a need for an arrangement for detecting errors in instructions sent to control JTAG components which does not require component pins or connections in addition to the normal connections required for standard JTAG operations.